The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2008

Filed:

Apr. 21, 2006
Applicants:

Seiki Ogura, Wappingers Falls, NY (US);

Kimihiro Satoh, Hopewell Junction, NY (US);

Tomoya Saito, Beacon, NY (US);

Inventors:

Seiki Ogura, Wappingers Falls, NY (US);

Kimihiro Satoh, Hopewell Junction, NY (US);

Tomoya Saito, Beacon, NY (US);

Assignee:

Halo LSI, Inc., Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.


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