The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2008

Filed:

Mar. 04, 2005
Applicant:

Vincent Hool, Fremont, CA (US);

Inventor:

Vincent Hool, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as compared to a reference integrated circuit, includes first and second sets of interconnection elements to connect to a package substrate. The first and second sets have matching arrangements, and corresponding interconnection elements of the first and second set have consistent functional assignments. The first and second sets include interconnection elements of mixed functional assignments. The first set is disposed within an area matching a size and shape of the reference integrated circuit, while the second set is disposed outside the area. In a specific embodiment, the first set includes an I/O signal and is located in the core area.


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