The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2008

Filed:

Feb. 09, 2005
Applicants:

Jianjun Cao, Torrance, CA (US);

Paul Harvey, Chepstow, GB;

David Kent, South Wales, GB;

Robert Montgomery, South Glamorgan, GB;

Kyle Spring, Temecula, CA (US);

Inventors:

Jianjun Cao, Torrance, CA (US);

Paul Harvey, Chepstow, GB;

David Kent, South Wales, GB;

Robert Montgomery, South Glamorgan, GB;

Kyle Spring, Temecula, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/336 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.


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