Method for forming trench memory cell structures for drams

Abstract

One embodiment of the invention relates to a method for forming trench memory cell structures having trench capacitors and planar selection transistors. An implantation for forming a reinforcement implant for improving the electrical connection of a storage electrode of a trench capacitor to a first source/drain zone of the respective selection transistor is effected in a self-aligned manner with respect to gate stacks provided above a substrate surface of the semiconductor substrate. In order to form the reinforcement implant, the deposition process for a first insulator layer, from which dielectric spacer structures of the gate stacks emerge, is divided into at least two substeps, the implantation being preceded by application of a base layer of the first insulator layer, the layer thickness of which defines the distance between the reinforcement implant and the gate stacks. A covering layer of the first insulator layer that is provided after the implantation improves the dielectric properties of the spacer structures which insulate the gate stacks from bit contact structures to be provided between the gate stacks.