The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2008

Filed:

Jul. 17, 2006
Applicants:

Rudolf Rupp, Julbach, DE;

Werner Aigner, Pfarrkirchen, DE;

Friedrich Passek, Adlkofen, DE;

Inventors:

Rudolf Rupp, Julbach, DE;

Werner Aigner, Pfarrkirchen, DE;

Friedrich Passek, Adlkofen, DE;

Assignee:

Siltronic AG, Munich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor wafer has an edge region with no defects larger than or equal to 0.3 μm. The wafers are produced by a process, comprising (a) providing a semiconductor wafer having a rounded and etched edge; (b) polishing the edge of the semiconductor wafer, in which step the semiconductor wafer, which is held on a centrally rotating chuck and projects beyond the chuck and at least one polishing drum which is inclined by a specific angle with respect to the chuck, rotates centrally and is covered with a polishing cloth, are moved toward one another and pressed onto one another under a specific contact pressure with a polishing abrasive being supplied continuously; (c) cleaning the semiconductor wafer; (d) inspecting an edge region of the semiconductor wafer using an inspection unit; and (e) further processing the semiconductor wafer.


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