The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2008
Filed:
Aug. 04, 2005
Fan-chi Tseng, Shanghai, CN;
Fan-Chi Tseng, Shanghai, CN;
Grace Semiconductor Manufacturing Corporation, Shanghai, CN;
Abstract
A structure and method of forming a semiconductor material wafer comprising forming an ingot of semiconductor material. A first dielectric layer is formed on the surface of the ingot, and the surface of the first dielectric layer is larger than the surface of the ingot. A second dielectric layer is formed on the surface of the first dielectric layer, and the surface of the second dielectric layer is larger than the surface of the first dielectric layer. The semiconductor wafer structure comprises a slip core formed of a semiconductor material, a first annular portion, and a second annular portion. The slip core had a first outer peripheral. The first annular portion is adjacent to the first outer peripheral, and is formed of a first dielectric material. The first annular portion has a second outer peripheral being larger than the first outer peripheral. The second annular portion is adjacent to the second outer peripheral, and is formed of a second dielectric material. The second annular portion has a third outer peripheral being larger than the second outer peripheral. The present invention provides the first annular portion and the second annular portion to protect the wafer, thereby preventing wafer edge cracks.