The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
May. 17, 2005
Albert Birner, Dresden, DE;
Matthias Goldbach, Dresden, DE;
Albert Birner, Dresden, DE;
Matthias Goldbach, Dresden, DE;
Infineont Technologies AG, Munich, DE;
Abstract
In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semiconductor substrate in addition to the active areas formed by sections of a semiconductor substrate. The insulator structures are respectively established on a base section by which a tensile stress is induced in adjacent active areas. Insulator structures respectively next to a p-type FET are selectively provided with additional buffer layers by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions of the n-type FETs and for holes in the channel regions of the p-type FETs, and the functionality is improved both for the n-type FETs and for the p-type FETs.