The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2008

Filed:

Oct. 21, 2005
Applicants:

Yu-chung Chin, Chung-Li, TW;

Chao-hsing Huang, Nan-Tou Hsien, TW;

Wei-chou Wang, Shu-Lin, TW;

Kun-chuan Lin, Taipei, TW;

Inventors:

Yu-Chung Chin, Chung-Li, TW;

Chao-Hsing Huang, Nan-Tou Hsien, TW;

Wei-Chou Wang, Shu-Lin, TW;

Kun-Chuan Lin, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 31/112 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention provides a BiFET semiconductor device vertically integrating a FET and a HBT on the same substrate. The BiFET semiconductor device comprises a HBT structure, a high-resistivity structure, and a FET structure, sequentially formed in this order from bottom to top on a semi-insulating substrate. The high-resistivity structure comprises at least two layers. A first layer is on top of the HBT structure to provide the required high resistivity, while the second layer having a high purity is on top of the first layer to prevent the doped impurity in the first layer to affect the upper FET structure.


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