Method for forming non-volatile memory with inlaid floating gate

Abstract

A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate. Next a first conductive layer is conformally formed over the substrate and is planarized to expose the shallow trench isolation. Then an inter gate dielectric layer is formed over the first conductive layer and the shallow trench isolation. Finally a second conductive layer is formed over the inter gate dielectric layer.