The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7383418 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 03, 2008

Filed:

Sep. 01, 2004
Applicants:

Kenneth J. Janik, Beaverton, OR (US);

K S Venkatraman, Hillsboro, OR (US);

Anwar Rohillah, Hillsboro, OR (US);

Eric Sprangle, Portland, OR (US);

Ronak Singhal, Portland, OR (US);

Inventors:

Kenneth J. Janik, Beaverton, OR (US);

K S Venkatraman, Hillsboro, OR (US);

Anwar Rohillah, Hillsboro, OR (US);

Eric Sprangle, Portland, OR (US);

Ronak Singhal, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/34 (2006.01); G06F 9/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.


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