The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7382844 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 03, 2008

Filed:

Feb. 11, 2005
Applicants:

Charlie C. Hwang, Wappinger Falls, NY (US);

Timothy G. Mcnamara, Fishkill, NY (US);

Ching-lung Tong, Highland Mills, NY (US);

Wiren Dale Becker, Hyde Park, NY (US);

Inventors:

Charlie C. Hwang, Wappinger Falls, NY (US);

Timothy G. McNamara, Fishkill, NY (US);

Ching-Lung Tong, Highland Mills, NY (US);

Wiren Dale Becker, Hyde Park, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the 'time zero' of the chips.


Find Patent Forward Citations

Hwang, Charlie. (2008). Methods to self-synchronize clocks on multiple chips in a system (U.S. Patent No. 7382844). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7382844

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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