The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Dec. 26, 2006
Applicants:

Osamu Nagao, Yokkaichi, JP;

Yasuyuki Fukuda, Kamakura, JP;

Hideo Mukai, Tokyo, JP;

Inventors:

Osamu Nagao, Yokkaichi, JP;

Yasuyuki Fukuda, Kamakura, JP;

Hideo Mukai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a control order of non-selected blocks at the time of data erase operation of one or a plurality of blocks, the control gate line is controlled to ground potential at first, then subsequently, a transfer transistor of the non-selected blocks is set to be an off-state. Next, high voltage is supplied to the well region and the data of the selected block is erased. Then, the control gate line is charged to the voltage which is used, for instance, at the time of reading out, or to the voltage (Vcg) which is used at the verification (Vcg). After the control gate line is charged to Vcg, the erase voltage supplied to the well region is discharged. Then, the control gate line is returned to ground potential after completing the discharge of the well region, and thus the data erase operation of the block is completed.


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