The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2008

Filed:

Jun. 16, 2006
Applicants:

Alexander V. Veidenbaum, Irvine, CA (US);

Adrian Cristal Kestelman, Barcelona, ES;

Mateo Valero Cortes, Barcelona, ES;

Ruben Gonzalez Garcia, Barcelona, ES;

Inventors:

Alexander V. Veidenbaum, Irvine, CA (US);

Adrian Cristal Kestelman, Barcelona, ES;

Mateo Valero Cortes, Barcelona, ES;

Ruben Gonzalez Garcia, Barcelona, ES;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.


Find Patent Forward Citations

Veidenbaum, Alexander. (2008). Prediction based instruction steering to wide or narrow integer cluster and narrow address generation (U.S. Patent No. 7380105). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7380105

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…