The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Sep. 30, 2004
Sanu K. Mathew, Hillsboro, OR (US);
Mark A. Anders, Hillsboro, OR (US);
Sarvesh H. Kulkarni, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Sanu K. Mathew, Hillsboro, OR (US);
Mark A. Anders, Hillsboro, OR (US);
Sarvesh H. Kulkarni, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logiccarry-in and a logiccarry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.