Semiconductor memory device having a hierarchical bit line structure

Abstract

In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarrayis connected via a first transistor PCto a power source voltage, and via a second transistor NCto a ground voltage. A main bit line MBLj is connected via a third transistor PDto the power source voltage. The gate electrodes of the first transistor PCand the second transistor NCare connected to the main bit line MBLj, the gate electrode of the third transistor PDis connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLito Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.