The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2008

Filed:

Dec. 23, 2004
Applicants:

Colin S. Bill, Cupertino, CA (US);

Swaroop Kaza, Woburn, MA (US);

Tzu-ning Fang, Palo Alto, CA (US);

Stuart Spitzer, Lynnfield, MA (US);

Inventors:

Colin S. Bill, Cupertino, CA (US);

Swaroop Kaza, Woburn, MA (US);

Tzu-Ning Fang, Palo Alto, CA (US);

Stuart Spitzer, Lynnfield, MA (US);

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 17/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.


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