The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2008

Filed:

Apr. 27, 2005
Applicants:

Connie Pin-chin Wang, Mountain View, CA (US);

Zoran Krivokapic, Santa Clara, CA (US);

Suzette Keefe Pangrle, Cupertino, CA (US);

Robert Chiu, San Jose, CA (US);

LU You, San Jose, CA (US);

Inventors:

Connie Pin-Chin Wang, Mountain View, CA (US);

Zoran Krivokapic, Santa Clara, CA (US);

Suzette Keefe Pangrle, Cupertino, CA (US);

Robert Chiu, San Jose, CA (US);

Lu You, San Jose, CA (US);

Assignees:

Spansion LLC, Sunnyvale, CA (US);

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.


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