The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
Mar. 30, 2006
Chih-hsiang Chen, Portland, OR (US);
Guo-qiang Lo, Singapore, SG;
Shih-ked Lee, Fremont, CA (US);
Integrated Device Technology, Inc., San Jose, CA (US);
Abstract
Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stackhaving a sidewall is formed over the gate dielectric layer. The gate stackcomprises a conductive layerand a hard maskoverlying the conductive layer. A lineris selectively deposited over the gate stacksuch that the lineris deposited on the hard maskat a rate lower than the rate of deposition on the conductive layer. Thus, the lineris substantially thinner on the hard maskthan on the conductive layer. A nitride spacer is formed overthe liner. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.