The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
Oct. 11, 2005
Jung-ho Moon, Seoul, KR;
Jae-min Yu, Seoul, KR;
Don-woo Lee, Gyeonggi-do, KR;
Chul-soon Kwon, Seoul, KR;
In-gu Yoon, Gyeonggi-do, KR;
Yong-sun Lee, Seoul, KR;
Jae-hyun Park, Gyeonggi-do, KR;
Jung-Ho Moon, Seoul, KR;
Jae-Min Yu, Seoul, KR;
Don-Woo Lee, Gyeonggi-do, KR;
Chul-Soon Kwon, Seoul, KR;
In-Gu Yoon, Gyeonggi-do, KR;
Yong-Sun Lee, Seoul, KR;
Jae-Hyun Park, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.