The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Sep. 30, 2005
Applicants:

Joo-byoung Yoon, Yongin-si, KR;

Jin-sung Kim, Suwon-si, KR;

Kyung-woo Lee, Suwon-si, KR;

Yeong-cheol Lee, Seoul, KR;

Sang-jun Park, Suwon-si, KR;

Hwan-shik Park, Seoul, KR;

Inventors:

Joo-Byoung Yoon, Yongin-si, KR;

Jin-Sung Kim, Suwon-si, KR;

Kyung-Woo Lee, Suwon-si, KR;

Yeong-Cheol Lee, Seoul, KR;

Sang-Jun Park, Suwon-si, KR;

Hwan-Shik Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.


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