Semiconductor memory device and error correction method thereof

Abstract

A semiconductor memory device includes a memory array having a data area and a check code area and a refresh control for controlling a refresh operation in a data holding state. The device also includes an operation system for executing an encoding operation for generating the check code using a bit string in the data area and a decoding operation for performing the error detection/correction of the data using the check code. Additionally, the device includes an encode controller for controlling an encode process in which, in a change to the data holding state, a first and second code are written in the check code area. Furthermore, the device includes a decode controller for controlling a decode process in which, at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.