The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Jun. 29, 2006
Koichi Seki, Hino, JP;
Takeshi Wada, Akishima, JP;
Tadashi Muto, Iruma, JP;
Kazuyoshi Shoji, Akishima, JP;
Yasurou Kubota, Akishima, JP;
Hitoshi Kume, Musashino, JP;
Koichi Seki, Hino, JP;
Takeshi Wada, Akishima, JP;
Tadashi Muto, Iruma, JP;
Kazuyoshi Shoji, Akishima, JP;
Yasurou Kubota, Akishima, JP;
Hitoshi Kume, Musashino, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.