The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Dec. 15, 2005
Ramona Winter, Munich, DE;
Susanne Lachenmann, Munich, DE;
Valentin Rosskopf, Poettmes-Schorn, DE;
Sibina Sukman-praehofer, Munich, DE;
Ramona Winter, Munich, DE;
Susanne Lachenmann, Munich, DE;
Valentin Rosskopf, Poettmes-Schorn, DE;
Sibina Sukman-Praehofer, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to a semiconductor wafer () having a plurality of first sawing regions (-) running parallel to one another in a first direction (X) and a plurality of second sawing regions (-) running parallel to one another in a second direction (Y), having useful regions () which in each case contain an integrated circuit () and which are in each case arranged between respective adjacent first sawing regions (-) and respective adjacent second sawing regions (-), and at least one test structure region arranged in the first sawing regions (-) and the second sawing regions (-) with test structures formed therein for checking electrical parameters of semiconductor elements. Connection contacts (-) connected to the test structures are provided in the test structure region, which connection contacts form a first row (R) and a second row (R), which in each case run in a longitudinal direction (L) and are offset relative to one another in the longitudinal direction (L) and transversely with respect to the longitudinal direction (L).