The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2008

Filed:

May. 11, 2004
Applicant:

Tae-sung Yoon, Cheonan-si, KR;

Inventor:

Tae-Sung Yoon, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/44 (2006.01); H01L 23/28 (2006.01); H01L 23/29 (2006.01); H01L 23/544 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.


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