Bus performance evaluation method for algorithm description

Abstract

The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation program structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general-purpose high-level language such as the C language and C++ language. In the simulation program structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is finally produced. That is, the result of the bus performance evaluation process is fed back to the simulation program structuring process such that isolation of the hardware and software is optimized in response to the bus traffic for the processing rate of the bus. This brings exclusion of feedback loops derived from the cooperative verification after the actual coding, so it is possible to considerably reduce overall turnaround time of design.