The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2008

Filed:

Dec. 14, 2004
Applicants:

Akio Sugi, Nagano, JP;

Naoto Fujishima, Nagano, JP;

Mutsumi Kitamura, Nagano, JP;

Katsuya Tabuchi, Nagano, JP;

Setsuko Wakimoto, Nagano, JP;

Inventors:

Akio Sugi, Nagano, JP;

Naoto Fujishima, Nagano, JP;

Mutsumi Kitamura, Nagano, JP;

Katsuya Tabuchi, Nagano, JP;

Setsuko Wakimoto, Nagano, JP;

Assignee:

Fuji Electric Co., Ltd., Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.


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