The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
Apr. 20, 2006
Kevin C. Gower, Lagrangeville, NY (US);
Bruce Hazelzet, Essex Junction, VT (US);
Mark W. Kellogg, Poughkeepsie, NY (US);
David J. Perlman, Wappingers Falls, NY (US);
Kevin C. Gower, Lagrangeville, NY (US);
Bruce Hazelzet, Essex Junction, VT (US);
Mark W. Kellogg, Poughkeepsie, NY (US);
David J. Perlman, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.