The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2008

Filed:

Sep. 24, 2004
Applicants:

Hirotaka Nishizawa, Fuchu, JP;

Kenji Osawa, Hachioji, JP;

Hideo Koike, Yokohama, JP;

Junichiro Osako, Kodaira, JP;

Tamaki Wada, Higashimurayama, JP;

Inventors:

Hirotaka Nishizawa, Fuchu, JP;

Kenji Osawa, Hachioji, JP;

Hideo Koike, Yokohama, JP;

Junichiro Osako, Kodaira, JP;

Tamaki Wada, Higashimurayama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K 19/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes external interface terminals and processing circuits, and couples to an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for at least a predetermined time period since the separation of an extraction detecting terminal from a corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. These power source feeding terminals are a power source terminal and a ground terminal, and any power source compensating capacitor is not connected between the power source terminal and the ground terminal.


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