The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2008
Filed:
Jul. 15, 2005
Chun-hsiung Hung, Hsinchu, TW;
Chuan-ying Yu, Taichung, TW;
Han-sung Chen, Hsinchu, TW;
Nai-ping Kuo, Hsinchu, TW;
Ching-chung Lin, Taipei County, TW;
Kuen-long Chang, Taipei, TW;
Chun-Hsiung Hung, Hsinchu, TW;
Chuan-Ying Yu, Taichung, TW;
Han-Sung Chen, Hsinchu, TW;
Nai-Ping Kuo, Hsinchu, TW;
Ching-Chung Lin, Taipei County, TW;
Kuen-Long Chang, Taipei, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.