Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches

Abstract

Improved methods of manufacturing semiconductor devices are provided to reduce dielectric loss in isolation trenches of the devices. In one example, a method of manufacturing a semiconductor device includes forming a plurality of shallow trench isolation (STI) trenches in a substrate. A tunnel oxide layer, a first conductive layer, a gate dielectric layer, and a second conductive layer are formed above the substrate. The layers are etched to delineate a plurality of stacked gate structures. In particular, the etching may include: performing a first etch of the second conductive layer, wherein at least a portion of the second conductive layer above the STI trenches remains following the first etch; and performing a second etch of the second conductive layer, wherein the remaining portion of the second conductive layer above the STI trenches and portions of the gate dielectric layer above the STI trenches are completely removed by the second etch.