The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2008
Filed:
Jun. 21, 2005
Dong-suk Shin, Yongin-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Ueno Tetsuji, Suwon-si, KR;
Ho Lee, Cheonan-si, KR;
Seung-hwan Lee, Suwon-si, KR;
Dong-suk Shin, Yongin-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Ueno Tetsuji, Suwon-si, KR;
Ho Lee, Cheonan-si, KR;
Seung-hwan Lee, Suwon-si, KR;
Abstract
In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.