The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2008

Filed:

Aug. 17, 2004
Applicants:

John G. Ferguson, Tualatin, OR (US);

Fedor G. Pikus, Beaverton, OR (US);

Kyohei Sakajiri, Portland, OR (US);

Laurence W. Grodd, Portland, OR (US);

Inventors:

John G. Ferguson, Tualatin, OR (US);

Fedor G. Pikus, Beaverton, OR (US);

Kyohei Sakajiri, Portland, OR (US);

Laurence W. Grodd, Portland, OR (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H04L 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses). For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules.


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