Apparatus and method for pipelined memory operations

Abstract

A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.