The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2008

Filed:

Jun. 30, 2004
Applicant:

Bryan C. Lagos, Danvers, MA (US);

Inventor:

Bryan C. Lagos, Danvers, MA (US);

Assignee:

Axcelis Technologies, Inc., Beverly, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01T 23/00 (2006.01); H01G 7/02 (2006.01); H05F 3/00 (2006.01); G03G 15/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is directed to a J-R electrostatic clamp (ESC) and method for forming same. The ESC comprises a ceramic layer for clamping a wafer thereto, and a plurality of electrodes arranged across the ceramic layer in an interior region and a peripheral region of the backside surface, wherein a plurality of electrode groups are defined by electrodes in the interior regions and peripheral regions. A first insulating layer generally isolates the electrode groups from one another, and an interconnect layer comprising a plurality of electrically conductive vias and interconnects electrically connect the electrodes associated with each respective electrode group. Each electrode group comprises a connection node, wherein the respective electrode group is operable to connect to a respective voltage potential. A second insulating layer generally encapsulates the interconnect layer. The method comprises patterning the electrodes, first insulating layer, interconnect layer, and second insulating layer to form the ESC.


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