The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2008

Filed:

Nov. 07, 2003
Applicants:

Gurpreet Bhullar, Nepean, CA;

Graham Allan, Stittsville, CA;

Inventors:

Gurpreet Bhullar, Nepean, CA;

Graham Allan, Stittsville, CA;

Assignee:

Mosaid Technologies Incorporated, Kanata, Ontario, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.


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