The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2008

Filed:

Sep. 22, 2004
Applicants:

Jianping Xu, Portland, OR (US);

Kyehyung Lee, Corvallis, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

David Rennie, Etobicoke, CA;

Tanay Karnik, Portland, OR (US);

Inventors:

Jianping Xu, Portland, OR (US);

KyeHyung Lee, Corvallis, OR (US);

Fabrice Paillet, Hillsboro, OR (US);

David Rennie, Etobicoke, CA;

Tanay Karnik, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.


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