The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2008
Filed:
Apr. 21, 2004
Sadami Takeoka, Osaka, JP;
Mitsuyasu Ohta, Osaka, JP;
Osamu Ichikawa, Osaka, JP;
Masayoshi Yoshimura, Kyoto, JP;
Sadami Takeoka, Osaka, JP;
Mitsuyasu Ohta, Osaka, JP;
Osamu Ichikawa, Osaka, JP;
Masayoshi Yoshimura, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.