The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2008

Filed:

May. 17, 2006
Applicants:

Gregory M. Daly, Seattle, WA (US);

Dan Willis, Portland, OR (US);

Inventors:

Gregory M. Daly, Seattle, WA (US);

Dan Willis, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/00 (2006.01); H05K 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A apparatus is described herein for configuring Input/Output (I/O) conductors on an integrated circuit (IC) or in a socket. At least a portion of the I/O conductors for an IC and/or contacts/receptacles of a socket are configured in a repeatable 2×4 rectangular T pattern. The rectangular T pattern includes a first line of four conductors, which include two ground conductors and a first differential pair of conductors, and a second line of four conductors, which include a second and a third pair of differential conductors. The I/O conductors on the IC may be pads/lands in an land-grid-array (LGA) style socket, pins in a pin-grid-array (PGA) style socket, or other conductor in another style of socket, while the socket includes corresponding contacts, receptacles, etc.


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