The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Jun. 30, 2005
Choupin B. Huang, San Jose, CA (US);
Charles T. Ballou, Columbia, SC (US);
Ramesh K. R. Velugoti, Bangalore, IN;
Drin-guang W. Chen, Irmo, SC (US);
Choupin B. Huang, San Jose, CA (US);
Charles T. Ballou, Columbia, SC (US);
Ramesh K. R. Velugoti, Bangalore, IN;
Drin-Guang W. Chen, Irmo, SC (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and arrangements to gang differential clock signals to attenuate pin-to-pin output skew for a clock driver are disclosed. Embodiments may comprise a pattern of conductors to interconnect output pins for differential clock signals with termination resistors. The pattern of conductors comprises a group of conductors for a positive clock (p-clock) signal and a group of conductors for a negative clock (n-clock) signal. The conductors for the p-clock signal intersect at a gang point between the output pins and pads for the termination resistors. Similarly, the conductors for the n-clock signals intersect at a gang point between the pins and the pads. In many embodiments, the distance between the pins and pads may be approximately 120 mils. In further embodiments, the distance may be longer or shorter than 120 mils. Other embodiments are disclosed and claimed.