The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2008

Filed:

Jun. 24, 2004
Applicants:

Dinesh Maheshwari, Fremont, CA (US);

Andrew Wright, Fremont, CA (US);

Inventors:

Dinesh Maheshwari, Fremont, CA (US);

Andrew Wright, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Built-in self-test (BIST) devices and methods are disclosed. A BIST section () according to one embodiment can include a built-in seed value memory () that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory () to a test pattern generator () to generate multiple test patterns for scan chains (-to-). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.


Find Patent Forward Citations

Maheshwari, Dinesh. (2008). Automatic built-in self-test of logic with seeding from on-chip memory (U.S. Patent No. 7346823). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7346823

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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