The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Oct. 13, 2005
Naoki Hirasawa, Okazaki, JP;
Sadahisa Onimaru, Chiryu, JP;
Hirohito Matsui, Okazaki, JP;
Kuniaki Mamitsu, Okazaki, JP;
Naohiko Hirano, Okazaki, JP;
Naoki Hirasawa, Okazaki, JP;
Sadahisa Onimaru, Chiryu, JP;
Hirohito Matsui, Okazaki, JP;
Kuniaki Mamitsu, Okazaki, JP;
Naohiko Hirano, Okazaki, JP;
DENSO CORPORATION, Kariya, JP;
Nippon Soken, Inc, Nishio, JP;
Abstract
A semiconductor device includes: a base member; a solder layer; and a semiconductor chip disposed on the base member through the solder layer. The chip has an in-plane temperature distribution when the chip is operated. The chip has an allowable maximum temperature as a temperature limit of operation. The in-plane temperature distribution of the chip provides a temperature of the chip at each position of a surface of the chip. The temperature margin at each position is obtained by subtracting the temperature of the chip from the allowable maximum temperature. The solder layer has an allowable maximum diameter of a void at each position, the void being disposed in the solder layer. The allowable maximum diameter of the void at each position becomes larger as the temperature margin at the position becomes larger.