The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Feb. 10, 2006
John Lam, Union City, CA (US);
Arch Zaliznyak, San Jose, CA (US);
Chong Lee, San Ramon, CA (US);
Rakesh Patel, Cupertino, CA (US);
Vinson Chan, Fremont, CA (US);
John Lam, Union City, CA (US);
Arch Zaliznyak, San Jose, CA (US);
Chong Lee, San Ramon, CA (US);
Rakesh Patel, Cupertino, CA (US);
Vinson Chan, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.