The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Dec. 21, 2004
Mark Ross, San Carlos, CA (US);
S. Babar Raza, San Jose, CA (US);
Dimitris Pantelakis, Austin, TX (US);
Anup Nayak, Fremont, CA (US);
Walter Bridgewater, San Jose, CA (US);
Mark Ross, San Carlos, CA (US);
S. Babar Raza, San Jose, CA (US);
Dimitris Pantelakis, Austin, TX (US);
Anup Nayak, Fremont, CA (US);
Walter Bridgewater, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A clock detection and selection circuit () can include a first counter (-) that generates a first count value CNTaccording to a first clock signal CLKand a second counter (-) that generates a second count value CNTaccording to a second clock signal CLK. First separation-detect logic (-) and second separation-detect logic (-) determine if a pre-specified difference exists between a first count value (CNT/CNT') and second count value (CNT/CNT′). According to such determinations, separation information (INFand INF) can be generated indicating which clock signal (CLKor CLK) is faster. Selection logic () can select a faster of the clock signals (CLKor CLK) if the separation information values confirm one another.