The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Jul. 20, 2006
Taku Kanaoka, Hitachinaka, JP;
Masashi Sahara, Hitachinaka, JP;
Yoshio Fukayama, Ichinomiya, JP;
Yutaro Ebata, Mito, JP;
Kazuhisa Higuchi, Tachikawa, JP;
Koji Fujishima, Kofu, JP;
Taku Kanaoka, Hitachinaka, JP;
Masashi Sahara, Hitachinaka, JP;
Yoshio Fukayama, Ichinomiya, JP;
Yutaro Ebata, Mito, JP;
Kazuhisa Higuchi, Tachikawa, JP;
Koji Fujishima, Kofu, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.