Electrical node of transistor and method of forming the same

Abstract

According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region. An impurity region may be formed in the semiconductor substrate below the buried contact hole. A contact hole spacer covering the sidewall of the buried contact hole may be formed. A buried conductive layer which covers the contact hole spacer and fills the buried contact hole may be formed.