The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2008

Filed:

Dec. 13, 2005
Applicants:

Byung-yong Choi, Suwon-si, KR;

Chang-woo OH, Suwon-si, KR;

Dong-gun Park, Seongnam-si, KR;

Dong-won Kim, Seongnam-si, KR;

Yong-kyu Lee, Guri-si, KR;

Inventors:

Byung-yong Choi, Suwon-si, KR;

Chang-woo Oh, Suwon-si, KR;

Dong-gun Park, Seongnam-si, KR;

Dong-won Kim, Seongnam-si, KR;

Yong-kyu Lee, Guri-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.


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