The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2008
Filed:
Apr. 05, 2005
Ming LI, Cupertino, CA (US);
Kevin Cunningham, Palo Alto, CA (US);
Sheeba Panayil, Santa Clara, CA (US);
Guangcai Xing, Fremont, CA (US);
R. Suryanarayanan Iyer, Santa Clara, CA (US);
Ming Li, Cupertino, CA (US);
Kevin Cunningham, Palo Alto, CA (US);
Sheeba Panayil, Santa Clara, CA (US);
Guangcai Xing, Fremont, CA (US);
R. Suryanarayanan Iyer, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in semiconductor devices. In one aspect, a two step deposition process is provided to form a nanocrystalline grain-sized polysilicon layer with a reduced roughness.