The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2008
Filed:
Mar. 20, 2006
Eung-rim Hwang, Kyoungki-do, KR;
Se-aug Jang, Kyoungki-do, KR;
Tae-woo Jung, Kyoungki-do, KR;
Seo-min Kim, Kyoungki-do, KR;
Woo-jin Kim, Kyoungki-do, KR;
Hyung-soon Park, Kyoungki-do, KR;
Young-bog Kim, Kyoungki-do, KR;
Hong-seon Yang, Kyoungki-do, KR;
Hyun-chul Sohn, Kyoungki-do, KR;
Eung-Rim Hwang, Kyoungki-do, KR;
Se-Aug Jang, Kyoungki-do, KR;
Tae-Woo Jung, Kyoungki-do, KR;
Seo-Min Kim, Kyoungki-do, KR;
Woo-Jin Kim, Kyoungki-do, KR;
Hyung-Soon Park, Kyoungki-do, KR;
Young-Bog Kim, Kyoungki-do, KR;
Hong-Seon Yang, Kyoungki-do, KR;
Hyun-Chul Sohn, Kyoungki-do, KR;
Hynix Semiconductor Inc., , KR;
Abstract
Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.