The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2008

Filed:

Jun. 03, 2005
Applicants:

Bhanwar Singh, Morgan Hill, CA (US);

Qiaolin Zhang, Albany, CA (US);

Iraj Emami, Austin, TX (US);

Joyce S. Oey Hewett, Austin, TX (US);

Luigi Capodiece, Santa Cruz, CA (US);

Inventors:

Bhanwar Singh, Morgan Hill, CA (US);

Qiaolin Zhang, Albany, CA (US);

Iraj Emami, Austin, TX (US);

Joyce S. Oey Hewett, Austin, TX (US);

Luigi Capodiece, Santa Cruz, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.


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