The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2008

Filed:

Jan. 31, 2003
Applicants:

Philippe Gendrier, Grenoble, FR;

Cyrille Dray, Eybens, FR;

Richard Fournel, Lumbin, FR;

Sébastien Poirier, Vizille, FR;

Daniel Caspar, Saint Hilaire du Touvet, FR;

Philippe Candelier, Saint Mury Monteymond, FR;

Inventors:

Philippe Gendrier, Grenoble, FR;

Cyrille Dray, Eybens, FR;

Richard Fournel, Lumbin, FR;

Sébastien Poirier, Vizille, FR;

Daniel Caspar, Saint Hilaire du Touvet, FR;

Philippe Candelier, Saint Mury Monteymond, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.


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